1. Field of the Invention
The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming a semiconductor device having a plug structure.
2. Description of the Prior Art
In recent years, the critical dimension (CD) in semiconductor processes has become finer with the increasing miniaturization of semiconductor devices. However, as the CD of the semiconductor device is continuously shrunk, the integrated process of forming a semiconductor device having metal gate also faces more challenges and limitations.
As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of highly integrated and high-speed operation, current techniques utilize miniaturized through holes and inter-layer dielectric layers to form a multilayered interconnected wiring structure to electrically connect a metal gate and source/drain regions of a transistor, thereby providing signal input/output pathways for the transistor. However, the current photoresist and lithography techniques are no longer qualified enough to support the currently integrated process while forming the metal gate and contact plug. For example, the position shift of the contact plug electrically connected to the source/drain regions easily occurs, which may directly penetrate the metal gate, thereby affecting the electrical performance of the entire device. For these reasons, how to efficiently improve the current structure of the semiconductor device, as well as the method of forming the same, has become an important task in this field.